Peripheral Component Interconnect (PCI) local bus is a common input/output (I/O) bus standard developed for higher end computer systems. PCI bus adapters are circuit boards and/or integrated circuit adapters that provide input/output I/O processing on the PCI bus and physical connectivity between servers and storage devices transferring 32 or 64 bit data at a clock speeds of 33 MHz or 66 MHz.
PCI-X bus, an enhancement to conventional PCI bus specification, increases bus capacity enabling systems and devices to operate at bus frequencies above 66 MHz and up to 133 MHz using 32 or 64 bit bus width. Many of the differences of the PCI-X bus from the PCI bus relate to bus operation, wait states and protocol enhancements. Card form factor, pin-outs, connector, bus widths and general protocols are the same. PCI-X components, such as bus interfaces, PC bridges and extenders, are backward compatible allowing such components to be operable in conjunction with conventional PCI components. However, in such cases the PCI-X bus is designed to revert back to conventional PCI mode and the operating frequency is adjusted to match that of the slowest device on the bus.
Manufacturers of PCI bus adapter boards routinely perform functional testing on PCI bus adapters so as to validate the functionality of the adapters during production. Such functionality tests are achieved by connecting the adapter board to be tested to a server or host machine and running a test program on the host machine to control power and signals to the connected adapter board. The adapter board is connected to the host machine using an isolated test slot which enables the adapter board to be added and removed without powering down the entire host system. Such a technique enables functional testing to be performed without having to use expensive steps and provides substantial time and labor savings during production testing.
A known isolation test slot used in existing manufacturing test systems for testing PCI and/or PCI-X bus adapters consists of a stackup of boards; an bus isolation extender, such as for example a ADEX™ isolation extender, stacked on the motherboard, followed by a riser card stacked on the isolation extender and a wearout connector stacked on the riser card. The riser card and the wearout extender serve to protect the connector of the bus isolation extender from being worn out by repeated insertions of the bus adapters for testing and ensure that the bus is extended outside the host machine to facilitate insertion and removal of the PCI/PCI-X adapters.
One major drawback of the aforementioned existing test systems is that the systems are incapable of validating PCI-X adapters operating at PCI-X clock rates, that is, rates up to 133 MHz. In fact, PCI-X adapters can only be tested by such test systems at clock speeds of 33 MHz or 66 MHz, that is, at PCI clock rates, even though the PCI-X bus adapters are capable of operating up to the higher 133 MHz clock rates.
There is, therefore, a need to provide a test system and methodology for testing the functionality of PCI/PCI-X bus adapters which is capable of testing PCI-X adapters operating at higher PCI-X rates in a reliable manner.
The embodiments disclosed herein therefore directly address the shortcomings of known techniques for testing PCI/PCI-X bus adapters by providing a system and methodology which ensures that PCI-X adapters can be tested at required PCI-X rates, that is, at clock rates higher than standard 33 MHz-66 MHz PCI rates.